A student writes:

	Hi Dr. Patt. In the corrections for appendix c, it says the following:

	in state 20:
	PC <- BaseR
	R7 <- PC

	in state 21:
	PC <- PC + LSHF(SEXT(0ff11),1)
	R7 <- PC

	if we are to do this, then R7 would contain  the address of the 
	subroutine, rather than the address of the point where the program is to
	resume its normal operation. 
	Or does the order of statements in the state doesn't matter?

	Sincerely yours,
	<<name withheld to protect the sequentio-phile>>

That is an excellent question.  Thank you for it.

The short answer: The order does not matter.

Now for the long answer.

I guess I did not make it clear.  During a clock cycle, there is a lot of logic that 
is processing simultaneously.  Unfortunately, when you write your simulator using an 
imperative language, your instructions get executed in sequence.  Therefore, you have 
to be careful that nothing in your code violates the fact that all computations are 
going on concurrently.  

In state 21, for example:

PC + LSHF(...  is being computed during the cycle.  Simultaneously the PC is
(vacuously) being computed.  At the end of the cycle, PC gets loaded with the result 
of the first, R7 gets loaded with the result of the second.

It is NOT the case that PC is computed first and THEN that value of PC is used to load 
into R7.  

Let me say it another way.  State changes do not happen in the middle of a cycle.  
All processing (combinational logic) happens concurrently and throughout the cycle.  
State changes (in the case of state 21, PC and R7) happen at the END of the cycle using 
the values that have been produced during the cycle.

The cycle has to be long enough for these computations to complete.

I guess if we had reversed the order of the two items in state 21, you would not have had 
any question.  ...and you would have come away from this with some incorrect assumptions.  
So, I am glad we did it the way we did, ...so you could ask, and I could answer.

One more thing.  Since the individual computations are using the state information at the 
beginning of the cycle, and (as in the case of state 21) you may need to read and write a
register in the same cycle, the writes MUST come at the end of the cycle.  Transparent 
latches won't work!  You need edge-triggered devices.  (Yes, they will work if you restrict
 the processing to half of the cycle and use transparent latches in the context of 
master-slave flipflops, but here we are considering allowing the processing to use the 
entire clock cycle, less set-up time.)  In fact, if you built this out of transparent 
latches, it is not clear what your PC <-- PC + $&%@  will produce.  Depends on how many 
times you cycle through the propagation delays before the clock cycle ends!

Got it!

Good luck.

Yale Patt