A student writes: Hi Dr Patt, I have a question here... I understand that all the latching happens at the end of the cycle. That is both the R7 and the PC are latched in the same cycle then don't we still need to ensure that one happens before the other?(PC is latched to the BUS so there seems to be some order between the signals LD.PC and GatePC. ) Nope. Both signals are asserted for the entire cycle. The GatePC signal ensures that the contents of PC are on the bus throughout the entire cycle. The LD.x signals are asserted throughout the cycle, but they affect the latches they enable at the END of the cycle, or rather on the leading edge of the clock of the next cycle. Thanks Regards <>