- indicates an invalid instruction in the corresponding stage (i.e. a pipeline bubble)

At the end		   Contents of pipeline latches
of cycle	DE latches   AGEX latches   MEM latches   SR latches

   1		    -		  -		-	     -	   (icache miss)
   2		    AND 	  -		-	     -
   3		    BRz	          AND		-	     -	   
   4		    BRz		  -		AND	     -	   (dep.stall, br.stall)
   5		    BRz		  -		-	     AND   (dep.stall, br.stall)
   6		    BRz		  -		-	     -	   (dep.stall, br.stall)
   7		    -		  BRz		-	     -	   (br.stall)
   8		    -		  -		BRz	     -	   (br.stall)
   9		    -		  -		-	     BRz   (br.stall)
   10		    ADD #10	  -		-	     -
   11		    HALT	  ADD #10	-	     -	
   12		    -		  HALT		ADD #10	     -	     (br.stall)
   13		    -		  -		HALT	     ADD #10 (br.stall)
   14		    -		  -		-	     HALT    (br.stall)
   15		    <---------------- HALTED --------------------->