- indicates an invalid instruction in the corresponding stage (i.e. a pipeline bubble)

At the end		   Contents of pipeline latches
of cycle	DE latches   AGEX latches   MEM latches   SR latches

   1		    -		  -		-	     -	   (icache miss)
   2		    ADD R0	  -		-	     -
   3		    ADD	R1	  ADD R0	-	     -	
   4		    ADD R2	  ADD R1	ADD R0	     -
   5		    ADD R3	  ADD R2	ADD R1	     ADD R0
   6		    HALT	  ADD R3	ADD R2	     ADD R1
   7		    -		  HALT		ADD R3	     ADD R2  (br.stall)  
   8		    -		  -		HALT	     ADD R3  (br.stall)
   9		    -		  -		-	     HALT    (br.stall)
   10		    <------------------ HALTED ------------------->