The University of Texas at Austin
Department of Electrical and Computer Engineering

Homework 2

EE 382N – Spring 2008
Yale N. Patt, Instructor
Rustam Miftakhutdinov, Aater Suleman, TAs
Due February 11th12th, 2008, beginning of discussion section

Part 1

Describe, using register transfer notation, the functionality of the following subset of the Intel x86 architecture:

You will need to refer to the x86 ISA manuals.

Part 2

On paper, design the data path and an accompanying state diagram to implement the subset of the x86 architecture described in Part 1 above.

Your state diagram should show all the relevant states. That is, pay careful attention to each phase of the instruction cycle, and all the processing that must go on to implement these instructions.

For this assignment, we will not be concerned with interrupts or traps/faults for illegal situations. (That comes later!)

Part 3

Now, implement your design from Part 2 in Verilog. You may use any available library parts for this assignment. All available libraries are in the following directory:

/home/projects/courses/spring_08/ee382n-16640/lib/

You may also access them online. These libraries include a 4-bit ALU slice. Please hand in all circuit diagrams for your design.

You may create dummy modules in Verilog to “generate” the control signals, such as the one shown below:

module ALU_control (alu_control_signals, opcode); 
   
   output [M:0] alu_control_signals;
   input  [N:0] opcode;
   
   assign       alu_control_signals  =  0;
   
endmodule // ALU_control

Use Verilog to simulate and verify that your design works for at least one instruction. You can choose any instruction and addressing mode. You may add dummy modules (for example memory) to test your datapath. Submit waveforms to demonstrate the working of your datapath.

Part 4

For the design in Part 2, select an instance of each of the five instructions and choose an appropriate addressing mode for each. Calculate the expected number of cycles required to execute each of those five instructions. Start counting cycles at the beginning of an instruction's fetch cycle and end with that instruction's completion (for example, destination write). For purposes of this assignment only, assume 10 ns cycle time, single cycle cache access, 100 ns memory access time, data cache hit ratio of 0.80, instruction cache hit ratio of 0.95. and no page faults. Please show your calculations.

Note that the actual number of cycles required to execute your program will be substantially fewer, since you will be able to overlap instruction execution. (That's what pipelining has been all about for more than 30 years). But, for this assignment only, we will examine the execution times of each instruction individually.