Note: This assignment is for your own use in planning your term project. It does not have to be turned in. However, we strongly encourage you to start work on this early. Doing this assignment will aid you in catching problems before they become major hassles.
Augment your datapath to handle the following:
CMOVC, JNE, JNBE, HLT, SAL, SAR, XCHG, PUSH, POP.PADDD, PSHUFW, MOVQ.Notes for SIMD instructions:
Notes for instructions operating on segment registers (these specifications override the x86 manuals for the purposes of this assignment and the project):
The MOV Seg, r/m and MOV r/m, Seg do not have an operand
size override prefix, yet are 16-bit operations. For
example, MOV EBX, CS updates the lower 16 bits of the value in EBX with
the value of CS, but does not change the upper 16 bits in EBX.
The PUSH Seg and POP Seg are 32-bit operations regardless of whether there
is an operand size override or not. For example, PUSH ES will always
decrement the ESP value by 4 and move 0x0000@ES[15:0] (where @ is a
concatenation) into the stack location ESP points to.
Show all control signals needed to control the augmented datapath. In Homework 4 we will start specifying the logic needed to produce those control signals.
Enter the additions of Part 1 above into your Verilog implementation.
To test your augmented specification, select five more instructions with appropriate addressing modes and prefixes. Calculate the number of cycles required to execute each of these five instructions. Your results will depend on your choices, of course. For purposes of this assignment, assume 10 ns cycle time, single-cycle cache access, 100 ns memory access time, data cache hit ratio of 0.80, instruction cache hit ratio of 0.95 and no page faults.