The University of Texas at Austin
Department of Electrical and Computer Engineering

List of Instructions for the Project

EE 382N – Spring 2008
Yale N. Patt, Instructor
Rustam Miftakhutdinov, Aater Suleman, TAs

Updated 03/02/08: fixed typo in the opcode of the 16 and 32 bit CMPXCHG instructions.

The following table contains all instruction variations you will implement in the project. It includes the instruction variations due to the operand size override and REP prefixes; in addition, many instructions may be preceded by a segment override prefix (consult the manuals for details).

OpcodeMnemonicDescription
04 ibADD AL,imm8Add imm8 to AL
05 iwADD AX,imm16Add imm16 to AX
05 idADD EAX,imm32Add imm32 to EAX
80 /0 ibADD r/m8,imm8Add imm8 to r/m8
81 /0 iwADD r/m16,imm16Add imm16 to r/m16
81 /0 idADD r/m32,imm32Add imm32 to r/m32
83 /0 ibADD r/m16,imm8Add sign-extended imm8 to r/m16
83 /0 ibADD r/m32,imm8Add sign-extended imm8 to r/m32
00 /rADD r/m8,r8Add r8 to r/m8
01 /rADD r/m16,r16Add r16 to r/m16
01 /rADD r/m32,r32Add r32 to r/m32
02 /rADD r8,r/m8Add r/m8 to r8
03 /rADD r16,r/m16Add r/m16 to r16
03 /rADD r32,r/m32Add r/m32 to r32
24 ibAND AL,imm8AL AND imm8
25 iwAND AX,imm16AX AND imm16
25 idAND EAX,imm32EAX AND imm32
80 /4 ibAND r/m8,imm8r/m8 AND imm8
81 /4 iwAND r/m16,imm16r/m16 AND imm16
81 /4 idAND r/m32,imm32r/m32 AND imm32
83 /4 ibAND r/m16,imm8r/m16 AND imm8 (sign-extended)
83 /4 ibAND r/m32,imm8r/m32 AND imm8 (sign-extended)
20 /rAND r/m8,r8r/m8 AND r8
21 /rAND r/m16,r16r/m16 AND r16
21 /rAND r/m32,r32r/m32 AND r32
22 /rAND r8,r/m8r8 AND r/m8
23 /rAND r16,r/m16r16 AND r/m16
23 /rAND r32,r/m32r32 AND r/m32
E8 cwCALL rel16Call near, relative, displacement relative to next instruction
E8 cdCALL rel32Call near, relative, displacement relative to next instruction
FF /2CALL r/m16Call near, absolute indirect, address given in r/m16
FF /2CALL r/m32Call near, absolute indirect, address given in r/m32
9A cpCALL ptr16:32Call far, absolute, address given in operand
FCCLDClear DF flag
0F 42 /rCMOVC r16, r/m16Move if carry (CF=1)
0F 42 /rCMOVC r32, r/m32Move if carry (CF=1)
0F B0 /rCMPXCHG r/m8,r8 Compare AL with r/m8. If equal, r/m8 = r8 and ZF=1. Else, ZF=0, AL=r/m8.
0F B1 /rCMPXCHG r/m16,r16 Compare AX with r/m16. If equal, r/m16 = r16 and ZF=1. Else, ZF=0, AX=r/m16.
0F B1 /rCMPXCHG r/m32,r32 Compare EAX with r/m32. If equal, r/m32 = r32 and ZF=1. Else, ZF=0, EAX=r/m32.
F4HLTHalt
FE /0INC r/m8Increment r/m byte by 1
FF /0INC r/m16Increment r/m word by 1
FF /0INC r/m32Increment r/m doubleword by 1
40+ rwINC r16Increment word register by 1
40+ rdINC r32Increment doubleword register by 1
CFIREtdInterrupt return (32-bit operand size)
77 cbJNBE rel8Jump short if not below or equal (CF=0 and ZF=0)
75 cbJNE rel8Jump short if not equal (ZF=0)
0F 87 cwJNBE rel16Jump near if not below or equal (CF=0 and ZF=0)
0F 87 cdJNBE rel32Jump near if not below or equal (CF=0 and ZF=0)
0F 85 cwJNE rel16Jump near if not equal (ZF=0)
0F 85 cdJNE rel32Jump near if not equal (ZF=0)
EB cbJMP rel8Jump short, relative, displacement relative to next instruction
E9 cwJMP rel16Jump near, relative, displacement relative to next instruction
E9 cdJMP rel32Jump near, relative, displacement relative to next instruction
FF /4JMP r/m16Jump near, absolute indirect, address given in r/m16
FF /4JMP r/m32Jump near, absolute indirect, address given in r/m32
EA cdJMP ptr16:16Jump far, absolute, address given in operand
EA cpJMP ptr16:32Jump far, absolute, address given in operand
88 /rMOV r/m8,r8Move r8 to r/m8
89 /rMOV r/m16,r16Move r16 to r/m16
89 /rMOV r/m32,r32Move r32 to r/m32
8A /rMOV r8,r/m8Move r/m8 to r8
8B /rMOV r16,r/m16Move r/m16 to r16
8B /rMOV r32,r/m32Move r/m32 to r32
8C /rMOV r/m16,SregMove segment register to r/m16
8E /rMOV Sreg,r/m16Move r/m16 to segment register
B0+ rbMOV r8,imm8Move imm8 to r8
B8+ rwMOV r16,imm16Move imm16 to r16
B8+ rdMOV r32,imm32Move imm32 to r32
C6 /0MOV r/m8,imm8Move imm8 to r/m8
C7 /0MOV r/m16,imm16Move imm16 to r/m16
C7 /0MOV r/m32,imm32Move imm32 to r/m32
0F 6F /rMOVQ mm, mm/m64Move quadword from mm/m64 to mm.
0F 7F /rMOVQ mm/m64, mmMove quadword from mm to mm/m64.
A4MOVS m8, m8Move byte at address DS:(E)SI to address ES:(E)DI
A5MOVS m16, m16Move word at address DS:(E)SI to address ES:(E)DI
A5MOVS m32, m32Move doubleword at address DS:(E)SI to address ES:(E)DI
F6 /2NOT r/m8Reverse each bit of r/m8
F7 /2NOT r/m16Reverse each bit of r/m16
F7 /2NOT r/m32Reverse each bit of r/m32
0F FD /rPADDW mm, mm/m64Add packed word integers from mm/m64 and mm.
0F FE /rPADDD mm, mm/m64Add packed doubleword integers from mm/m64 and mm.
0F ED /rPADDSW mm, mm/m64Add packed signed word integers from mm/m64 and mm and saturate the results.
58+ rwPOP r16Pop top of stack into r16; increment stack pointer
58+ rdPOP r32Pop top of stack into r32; increment stack pointer
1FPOP DSPop top of stack into DS; increment stack pointer
07POP ESPop top of stack into ES; increment stack pointer
17POP SSPop top of stack into SS; increment stack pointer
0F A1POP FSPop top of stack into FS; increment stack pointer
0F A9POP GSPop top of stack into GS; increment stack pointer
0F 70 /r ibPSHUFW mm1, mm2/mm64, imm8Shuffle the words in mm2/m64 based on the encoding in imm8 and store result in mm1.
FF /6PUSH r/m16Push r/m16
FF /6PUSH r/m32Push r/m32
50+rwPUSH r16Push r16
50+rdPUSH r32Push r32
6APUSH imm8Push imm8
68PUSH imm16Push imm16
68PUSH imm32Push imm32
0EPUSH CSPush CS
16PUSH SSPush SS
1EPUSH DSPush DS
06PUSH ESPush ES
0F A0PUSH FSPush FS
0F A8PUSH GSPush GS
F3 A4REP MOVS m8,m8Move (E)CX bytes from DS:[(E)SI] to ES:[(E)DI]
F3 A5REP MOVS m16,m16Move (E)CX words from DS:[(E)SI] to ES:[(E)DI]
F3 A5REP MOVS m32,m32Move (E)CX doublewords from DS:[(E)SI] to ES:[(E)DI]
C3RETNear return to calling procedure
CBRETFar return to calling procedure
C2 iwRET imm16Near return to calling procedure and pop imm16 bytes from stack
CA iwRET imm16Far return to calling procedure and pop imm16 bytes from stack
D0 /4SAL r/m8,1Multiply r/m8 by 2, once
D2 /4SAL r/m8,CLMultiply r/m8 by 2, CL times
C0 /4 ibSAL r/m8,imm8Multiply r/m8 by 2, imm8 times
D1 /4SAL r/m16,1Multiply r/m16 by 2, once
D3 /4SAL r/m16,CLMultiply r/m16 by 2, CL times
C1 /4 ibSAL r/m16,imm8Multiply r/m16 by 2, imm8 times
D1 /4SAL r/m32,1Multiply r/m32 by 2, once
D3 /4SAL r/m32,CLMultiply r/m32 by 2, CL times
C1 /4 ibSAL r/m32,imm8Multiply r/m32 by 2, imm8 times
D0 /7SAR r/m8,1Signed divide r/m8 by 2, once
D2 /7SAR r/m8,CLSigned divide r/m8 by 2, CL times
C0 /7 ibSAR r/m8,imm8Signed divide r/m8 by 2, imm8 times
D1 /7SAR r/m16,1Signed divide r/m16 by 2, once
D3 /7SAR r/m16,CLSigned divide r/m16 by 2, CL times
C1 /7 ibSAR r/m16,imm8Signed divide r/m16 by 2, imm8 times
D1 /7SAR r/m32,1Signed divide r/m32 by 2, once
D3 /7SAR r/m32,CLSigned divide r/m32 by 2, CL times
C1 /7 ibSAR r/m32,imm8Signed divide r/m32 by 2, imm8 times
FDSTDSet DF flag
90+rwXCHG AX,r16 Exchange r16 with AX
90+rdXCHG EAX,r32 Exchange r32 with EAX
86 /rXCHG r/m8,r8 Exchange r8 with r/m8
87 /rXCHG r/m16,r16 Exchange r16 with r/m16
87 /rXCHG r/m32,r32Exchange r32 with r/m32