Byte Addressable Little endian Big endian ISA Microarchitecture Addressability Data types Fixed point Unary Binary Decimal Virtual Machine Science of Trade-offs Fault tolerent computing Adders: Ripple carry, lookahead carry Fan-in Design points Transformation Hierarchy Design for high performance, low power, availability, security Caches - historically uArch now ISA Touch/Prefetch/Poststore instructions Determinism - Cray machines. S & T registers Memory Hierarchy Fast vs big run time vs compile time recompile at run-time x86 loop construct Probe instruction Fixed length vs Variable length Pipeline Flynn's bottleneck Fetch stage Decode stage Wimpy decoders Bits per instruction LD/ST Architectures Uniform decode Huffman encoding of istream Three kinds of instructions: operate, data movement, and control NAND is complete logic Test & Set Condition codes Condition code - Advantages and Disadvantages Steering bit 0-Address machine stack machine 1-Address machine Accumulator 2-Address machine 3-Address machine Special I/O instructions Memory mapped I/O Multiple condition code Compound predicate -- collapsing branch Memory mapped I/O More registers - Advantages and Disadvantages Power aware computing Precision architecture EditPC (VAX) Index instruction (VAX) IEEE Double Extended Capability based machine Bit vector Position independence Interrupt latency Realtime MIPS vectoring interrupts Processor status register RISC live out Register Spilling Addressing Modes Indirect addressing PC relative addressing Binning Overlaying the address space Performance equation Clock skew Wave-pipelining Critical path Speed path Cycles per instruction Bread & Butter design Hardwired vs. Microprogrammed Control ROM vs. PLA Control Store Diode "The Refrigerator" PSR Privilege vs. Priority Trace bit Compatability bit 1's catching property SRAM vs. DRAM Page mode Row Address Strobe Column Address Strobe Granularity Segment Registers DRAM refresh SECDED ECC bits (Parity/Checksum) Hamming Distance Interleaving memory Tristated outputs Unaligned access Virtual Memory Interleaving for concurrency Interleaving for hiding latency Thrashing Von Neuman Architecture Harvard Architecture Pages Frames Resident Access Control 4-levels of access Translation Working Set Balance Set Page Fault Faults vs. Traps Page Table Entry(PTE) Program Region Control Region Valid bit Protection bits Modified bit Reference bit Page replacement Physical Frame Number System Page Table Process Page Table Base Register Length Register