This first problem set will cover fundamental knowledge learned in the prerequisite courses, EE 319K and EE 360N. You are asked to do the logic design of a simple ALU. In this first problem set, you are asked to solve the problem with pencil and paper. In the next problem set, you will be asked to redo the problem using the Verilog CAD tools which we will be using for the rest of the semester.
This is the first step in your term project – the complete design of a substantial subset of a CPU and its simulation, from a formal specification to the gates that implement that specification.
Using only 2 input NAND gates (or NOR gates, your choice), design a 16-bit arithmetic logic unit that performs the following functions:
output[15:0] := a_input[15:0] + b_input[15:0]
output[15:0] := a_input[15:0] AND b_input[15:0]
output[15:0] := NOT(b_input[15:0])
output[15:0] := SAT(a_input[15:8], b_input[15:8]) @
SAT(a_input[7:0], b_input[7:0])Note that SAT is signed saturating addition and @ is concatenation. The
only cases where saturating addition differs from traditional addition is
when there is overflow. In the case of overflow, saturating addition will
cause the result to be the maximum representable value (of the same sign).
For instance in 4-bit signed addition, 4 + 4 = 7 (0100 + 0100 = 0111).
Note also that for the saturating addition there are two separate 8-bit
adds with no carry propagated between them.
First design a single bit “slice” of the ALU, then interconnect slices as appropriate to get the full 16-bit ALU.
For this first assignment, you may use whatever drawing standards you were taught in your prerequisite courses. Recall (or ask about) the advantages of hierarchical design. Also, you are expected to provide appropriate documentation of all your work. At the very least, your documentation should contain a paragraph summarizing the function of each component in your design and an overall summary describing the interaction of the major components. Good documentation will count substantially in the grading, and more importantly, will prove enormously useful in keeping track of your work in the course project.
What is the worst case delay for any single operation in your ALU (in gate delays)?
Explain how your ALU could be used, perhaps more than once (that is, using
more than one copy), to implement s := b - a, s := xor(a, b). Illustrate with a
drawing if you like.
It is always a good idea to keep copies of any drawings you turn in. For example, it will make life easier when you need to refer to them while you are doing Homework 1b.