Project Specification

Instructions

Please consult the list of instructions to be implemented (also available in PostScript format). The following is a quick summary of that list:

Note that the NOP instruction is a special case of the XCHG instruction.

Prefixes

• Operand Size Override
• Segment Register Override
• Repeat String operation (for MOVS only)

Addressing Modes

• Immediate
• Register
• Mod R/M Byte
• SIB Byte (except for Index==100 or Base==101)

Data Types

• Doubleword -- as specified by the instruction (doubleword is default)
• Word -- requires operand size override
• Byte -- as specified by the instruction
• Packed Double Word -- as specified by the SIMD instructions (64bit mm registers only)
• Packed Word -- as specified by the SIMD instructions (64bit mm registers only)

General Issues

• There will be no self-modifying code in the test cases.
• There will be no illegal operands in the test cases.

Addresses

An effective address is computed from the instruction, e.g., a base plus displacement specified with an r/m byte.

A linear address is calculated by summing the effective address with the appropriate segment register having been shifted 16 bits to the left for a total size of 32-bits.

Main Memory

Main memory is 32KB in size. The exact configuration is per your design. Please use the SRAM parts from the library to construct your main memory.

Caches

Instruction and data cache size is limited to 1KB of data storage total. The exact configurations are per your design. Please use RAM parts from the library to construct your tag and data stores. You may use register parts to construct the valid bits, so that they can be initialized to zero easily.

The Bus

A bus must connect the processor, main memory and your I/O devices. Its width and arbitration scheme are per your design.

Segmentation

Each segment has a constant (hardwired) segment limit associated with it. When an effective address exceeds the segment limit a general protection exception is taken (see Interrupts and Exceptions below for details). Be advised that when accessing a word, double word, or quad word, all the bytes in the data must fall within the segment limit.

Virtual Memory

You are required to implement parts of a virtual memory system as specified below.

The page size for your project is 4KB.

A Translation Lookaside Buffer (TLB) will be used to translate between virtual page numbers and physical frame numbers. Each TLB entry will contain at least the following flags: a valid bit, a present flag, and a read/write flag. Note a translation can be valid without the page being present in main memory, hence the valid and present flags. Depending on your design, you may or may not need a PCD flag (Page-level Cache Disable) for your I/O devices. See I/O Devices below.

A page can be in the “read only” state or in the “read or write state,” as indicated by the read/write flag.

The TLB will hold 8 entries, 6 of which will be hardcoded to values specified by your TA. The other two entries are per your design, e.g., memory mapped I/O or other project specific purposes.

If the processor tries to write a read only page, then a general protection exception is taken.If the processor tries to access a page not in the TLB or a page not present in physical memory, then a page fault is taken. (Note the abstraction: you are not required to implement the x86 page directory table for this project.)

I/O Devices

You are required to implement at least one simple and one complicated I/O device for your project. See the LC-3b documentation for simple examples of memory mapped keyboard and monitor registers. An example of a more complicated I/O device is a DMA controller. Be advised that memory addresses that correspond to memory mapped I/O devices cannot be cached. You can use the TLB to indicate that a page cannot be cached by setting the PCD flag (Page-level Cache Disable) in the TLB. In this case, you will issue the request to main memory directly.

Interrupts and Exceptions

You are required to support at least one external interrupt from one of your I/O devices. The two exceptions that you are required to support are the general protection exception and page fault. Note that both instruction and data accesses may cause these exceptions.

General protection exceptions are caused by writing to a read only page or when computing a memory operand with an effective address outside the CS, DS, ES, FS or GS segment limit. Note that accessing memory outside the stack segment(SS), limit causes a Stack Segment Exception which is not required for this project.

Page faults are caused by accessing a page that is not in the TLB or not present in physical memory.

There will be no nested interrupts/exceptions.

The procedure for transferring control to the interrupt and exception handler is the following:

1. Push EFLAGS.
2. Push CS.
3. Push EIP.
4. Determine the address of the Interrupt Descriptor Table (IDT) entry that contains the far pointer that points to the relevant service routine.
5. Load the new CS and EIP values and begin executing from the new location.

The IRETD instruction will appear at the end of the interrupt service routine and will pop the EIP, CS and EFLAGS registers.

The far pointer pointing to the service routine is found by indexing into the IDT with the interrupt or exception vector.

The IDTR register contains a pointer to the base address of the IDT. The value in the IDTR is a linear address. The IDTR register is actually a 6-byte register, where the first 4 bytes are the base address of the IDT and the final 2 bytes are the limit of the base address. You are not required to implement limit checking on the IDT. Therefore the first 4 bytes are all that you need to worry about for this project. IDTR will be hardwired at initialization time and won't change while the processor is running.

The vector number for the page fault is 14 and the vector number for general protection exception is 13.

If an instruction causes both a General Protection exception and a Page Fault, your machine should handle the General Protection exception and ignore the Page Fault.