• Stephen Pruett and Yale Patt,
"Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches,"
The 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2021.


• Siavash Zangeneh, Stephen Pruett, Sangkug Lym, and Yale Patt,
"BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches,"
The 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2020.


• José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, and Yale N. Patt,
"Improving the Performance of Object-Oriented Languages with Dynamic Predication of Indirect Jumps,"
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Seattle, WA, March 2008.


• Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert Cohn,
"VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization,"
Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA), San Diego, CA, June 2007.


• José A. Joao, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
"Dynamic Predication of Indirect Jumps,"
Computer Architecture Letters, Vol. 6, May 2007.


• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
"Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors,"
Proceedings of the 5th International Symposium on Code Generation and Optimization (CGO), San Jose, CA, March 2007.


• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
"Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication"
IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 27, No. 1, pages 94-104, January/February 2007.


• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
"Diverge-Merge Processor(DMP): Dynamic Predicated Execution of Complex Control-flow Graphs Based on Frequently Executed Paths"
Proceedings of the 39th ACM/IEEE International Symposium on Microarchitecture, Orlando, Florida, December 2006.


• Hyesoon Kim, M. Aater Suleman, Onur Mutlu, and Yale N. Patt,
"2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set,"
Proceedings of the 4th International Symposium on Code Generation and Optimization (CGO), pages 159-169, New York, NY, March 2006.


• Hyesoon Kim, Onur Mutlu, Jared Stark, and Yale N. Patt,
"Wish Branches: Enabling Adaptive and Aggressive Predicated Execution"
IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 26, No. 1, pages 48-58, January/February 2006.


• Hyesoon Kim, Onur Mutlu, Jared Stark, and Yale N. Patt,
"Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution,"
Proceedings of the 38th ACM/IEEE International Symposium on Microarchitecture, Barcelona, Spain, November 2005.


• David N. Armstrong, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
"Wrong Path Events: Exploiting Illegal and Unusual Program Behavior for Early Misprediction Detection and Recovery,"
Proceedings of the 37th ACM/IEEE International Symposium on Microarchitecture, Portland, Oregon, December 2004.


• Jared Stark, Marius Evers, and Yale N. Patt,
"Variable Length Path Branch Prediction,"
Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, October 1998.


• Marius Evers, Sanjay J. Patel, Robert S. Chappell, and Yale N. Patt,
"Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work,"
Proceedings of the 25th International Symposium on Computer Architecture, Barcelona, June 1998.


• Po-Yung Chang, Eric Hao, and Yale N. Patt,
"Target Prediction for Indirect Jumps,"
Proceedings of the 24th International Symposium on Computer Architecture, Denver, June 1997.


• Eric Sprangle, Robert S. Chappell, Mitch Alsup, and Yale N. Patt,
"The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference,"
Proceedings of the 24th International Symposium on Computer Architecture, Denver, June 1997.


• Po-Yung Chang, Marius Evers, and Yale N. Patt,
"Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference,"
International Journal of Parallel Programming, 1997, Vol 25, Num 5, pp. 339-362.


• Stephan Jourdan, Jared Stark, Tse-Hao Hsing, and Yale N. Patt,
"Recovery Requirements of Branch Prediction and Storage Structures in the Presence of Mispredicted-Path Execution,"
International Journal of Parallel Programming, 1997, Vol 25, Num 5, pp. 363-384.


• Stephan Jourdan, Tse-Hao Hsing, Jared Stark, and Yale N. Patt,
"The Effects of Mispredicted-Path Execution on Branch Prediction Structures,"
International Conference on Parallel Architectures and Compilation Techniques, Boston, MA, October 1996.


• Po-Yung Chang, Marius Evers, and Yale N. Patt,
"Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference,"
International Conference on Parallel Architectures and Compilation Techniques, Boston, MA, October 1996.


• Marius Evers, Po-Yung Chang, and Yale N. Patt,
"Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches,"
Proceedings, 23th International Symposium on Computer Architecture, Philadelphia, PA, May 1996.


• Po-Yung Chang, Eric Hao, and Yale N. Patt,
"Alternative Implementations of Hybrid Branch Predictors,"
Proceedings of the 28th ACM/IEEE International Symposium on Microarchitecture, Ann Arbor, MI, 1995.


• Po-Yung Chang, Eric Hao, Yale N. Patt, and Pohua Chang,
"Using Predicated Execution to Improve the Performance of a Dynamically-Scheduled Machine With Speculative Execution,"
International Journal of Parallel Programming, Vol.24, 1996.


• Po-Yung Chang, Eric Hao, Yale N. Patt, and Pohua Chang,
"Using Predicated Execution to Improve the Performance of a Dynamically-Scheduled Machine With Speculative Execution,"
International Conference on Parallel Architectures and Compilation Techniques, Limassol, Cyprus, June 1995.


• Po-Yung Chang, Eric Hao, Tse-Yu Yeh, and Yale Patt,
"Branch Classification: A New Mechanism for Improving Branch Predictor Performance,"
International Journal of Parallel Programming, Vol.24, 1996.


• Po-Yung Chang, Eric Hao, Tse-Yu Yeh, and Yale Patt,
"Branch Classification: A New Mechanism for Improving Branch Predictor Performance,"
Proceedings of the 27th International Symposium on Microarchitecture, San Jose, California, November 1994.


• Eric Hao, Po-Yung Chang, and Yale Patt,
"The Effect of Speculatively Updating Branch History on Branch Prediction Accuracy, Revisited,"
Proceedings of the 27th International Symposium on Microarchitecture, San Jose, California, November 1994.


• Tse-Yu Yeh and Yale N. Patt,
"Branch History Table Indexing to Prevent Pipeline Bubbles in Wide-Issue Superscalar Processors,"
Proceedings of the 26th International Symposium and workshop on Microarchitecture, Austin, TX, December 1993.


• Tse-Yu Yeh, Deborah Marr, and Yale Patt,
"Increasing Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache," (pdf)
Proceedings of the 7th ACM International Conference on Supercomputing, Tokyo, Japan, July 1993.


• Tse-Yu Yeh and Yale N. Patt,
"A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History,"
Proceedings, 20th International Symposium on Computer Architecture, San Diego, CA, May 1993.


• Tse-Yu Yeh and Yale Patt,
"A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution,"
Proceedings, 25th International Symposium and workshop on Microarchitecture, Portland OR, November 1992.


• Tse-Yu Yeh and Yale Patt,
"Alternative Implementations of Two-Level Adaptive Training Branch Prediction,"
Proceedings, 19th International Symposium on Computer Architecture, Queensland, Australia, May 1992.


• Tse-Yu Yeh and Yale Patt,
"Two-Level Adaptive Training Branch Prediction,"
Proceedings, 24th International Symposium and workshop on Microarchitecture, Albuquerque, November 1991.

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