• Siavash Zangeneh Kamali,
"Using Convolutionan Neural Networks to Improve Branch Prediction,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2022-002, August 2022.


• Stephen Pruett,
"Maintaining High Performance in the presence of Impossible-to-Predict Branches,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2022-001, May 2022.


• Ben (Ching-Pei) Lin,
"Mitigating Bank Conflicts in Main Memory via Selective Data Duplication and Migration,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2021-001, May 2021.


• Stephen Pruett, Yale N. Patt,
"Dynamic Merge Point Prediction,"
HPS Technical Report, TR-HPS-2020-001, May 2020.


• Siavash Zangeneh, Stephen Pruett, Sangkug Lym, Yale N. Patt,
"BranchNet: Using Offline Deep Learning To Predict Hard-To-Predict Branches,"
HPS Technical Report, TR-HPS-2019-002, August 2019.


• Faruk Guvenilir,
"Scalable Virtual Memory via Tailored and Larger Page Sizes,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2019-001, May 2019.


• Milad Hashemi,
"On-Chip Mechanisms to Reduce Effective Memory Access Latency,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2016-001, August 2016.


• Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt,
"Reducing Effective Memory Access Latency via an Enhanced (Compute Capable) Memory Controller,"
HPS Technical Report, TR-HPS-2015-001, September 2015.


• Rustam Miftakhutdinov,
"Performance Prediction for Dynamic Voltage and Frequency Scaling,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2014-004, August 2014.


• Khubaib,
"Performance and Energy Efficiency via an Adaptive MorphCore Architecture,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2014-002, July 2014.


• Carlos Villavieja, José A. Joao, Rustam Miftakhutdinov and Yale N. Patt,
"Yoga: A Hybrid Dynamic VLIW/OoO Processor"
HPS Technical Report, TR-HPS-2014-001, March 2014.


• Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,
"Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems,"
HPS Technical Report, TR-HPS-2012-001, February 2012.


• Chang Joo Lee, Eiman Ebrahimi, Veynu Narasiman, Onur Mutlu, and Yale N. Patt,
"DRAM-Aware Last-Level Cache Replacement,"
HPS Technical Report, TR-HPS-2010-007, December 2010.


• Veynu Narasiman, Chang Joo Lee, Michael Shebanow, Rustam Miftakhutdinov, Onur Mutlu, and Yale N. Patt,
"Improving GPU Performance via Large Warps and Two-Level Warp Scheduling,"
HPS Technical Report, TR-HPS-2010-006, December 2010.


• Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,
"Prefetch-Aware Shared-Resource Management for Multi-Core Systems,"
HPS Technical Report, TR-HPS-2010-005, December 2010.


• Chang Joo Lee,
"DRAM-Aware Prefetching and Cache Management,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2010-004, December 2010.


• M. Aater Suleman,
"An Asymmetric Multi-core Architecture for Efficiently Accelerating Critical Paths in Multithreaded Programs,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2010-003, May 2010.


• Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt,
"DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems,"
HPS Technical Report, TR-HPS-2010-002, April 2010.


• M. Aater Suleman, Moinuddin Qureshi, Khubaib, Yale N. Patt,
"Feedback Driven Pipelining,"
HPS Technical Report, TR-HPS-2010-001, March 2010.


• Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt,
"Techniques for Bandwidth-Efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems,"
HPS Technical Report, TR-HPS-2008-004, October 2008.


• M. Aater Suleman, Onur Mutlu, Moinuddin Qureshi, and Yale N. Patt,
"An Asymmetric Multi-core Architecture for Accelerating Critical Sections,"
HPS Technical Report, TR-HPS-2008-003, September 2008.


• Chang Joo Lee, Onur Mutlu, Veynu Narasiman, and Yale N. Patt,
"Prefetch-Aware DRAM Controllers,"
HPS Technical Report, TR-HPS-2008-002, September 2008.


• José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, and Yale N. Patt,
"Improving the Performance of Object-Oriented Languages with Dynamic Predication of Indirect Jumps,"
HPS Technical Report, TR-HPS-2008-001, January 2008.


• Hyesoon Kim,
"Adaptive Predication via Compiler-Microarchitecture Cooperation,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2007-003, August 2007.


• Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert S. Cohn,
  "VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization,"
  HPS Technical Report, TR-HPS-2007-002, March 2007.
  
  
• M. Aater Suleman, Yale N. Patt, Eric A. Sprangle, Anwar Rohillah, Anwar Ghuloum, and Doug Carmean,
"ACMP: Balancing Hardware Efficiency and Programmer Efficiency"
HPS Technical Report, TR-HPS-2007-001, February 2007.


• Chang Joo Lee, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
"A Performance-Aware Speculation Control Technique Using Wrong Path Usefulness Prediction"
HPS Technical Report, TR-HPS-2006-010, December 2006.


• Moinuddin K. Qureshi and Yale N. Patt,
"Utility-Based Cache Partitioning"
HPS Technical Report, TR-HPS-2006-009, September 2006.


• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
"Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-flow Graphs Based on Frequently Executed Paths"
HPS Technical Report, TR-HPS-2006-008, September 2006.


• Onur Mutlu,
"Efficient Runahead Execution Processors,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2006-007, July 2006.


• Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
"Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers,"
HPS Technical Report, TR-HPS-2006-006, May 2006.


• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
"Compiler-Assisted Dynamic Predicated Execution of Complex Control-Flow Structures,"
HPS Technical Report, TR-HPS-2006-005, April 2006.


• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
"Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses,"
HPS Technical Report, TR-HPS-2006-004, April 2006.


• Moinuddin K. Qureshi, Daniel Lynch, Onur Mutlu, and Yale N. Patt,
"A Case for MLP-Aware Cache Replacement,"
HPS Technical Report, TR-HPS-2006-003, 27 February 2006.


• Moinuddin K. Qureshi, David Thompson, Thomas R. Puzak, and Yale N. Patt,
"Line Distillation: A Mechanism to Improve Cache Utilization,"
HPS Technical Report, TR-HPS-2006-002, 16 February 2006.


• Hyesoon Kim, M. Aater Suleman, Onur Mutlu, and Yale N. Patt,
"2D-Profiling: Detecting Input-Dependent Branches With a Single Input Data Set,"
HPS Technical Report, TR-HPS-2006-001, January 2006.


• Mary D. Brown,
"Reducing Critical Path Execution Time by Breaking Critical Loops,"
Ph.D. Dissertation, HPS Technical Report, TR-HPS-2005-003, August 2005.


• Hyesoon Kim, Onur Mutlu, Jared Stark, David N. Armstrong, and Yale N. Patt,
"Wish Branch: A New Control Flow Instruction Combining Conditional Branching and Predicated Execution,"
HPS Technical Report, TR-HPS-2005-002, February 2005.


• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
"An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors,"
HPS Technical Report, TR-HPS-2005-001, January 2005.


• Moinuddin K. Qureshi, Onur Mutlu, and Yale N. Patt,
"Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors,"
HPS Technical Report, TR-HPS-2004-004, 3 December 2004.


• Moinuddin K. Qureshi, David Thompson, and Yale N. Patt,
"The V-Way Cache: Demand Based Associativity via Global Replacement,"
HPS Technical Report, TR-HPS-2004-003, October 2004.


• David N. Armstrong, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
"Wrong Path Events: Exploiting Illegal and Unusual Program Behavior for Early Misprediction Recovery,"
HPS Technical Report, TR-HPS-2004-002, June 2004.


• Mary D. Brown and Yale N. Patt,
"Demand-Only Broadcast: Reducing Register File and Bypass Power in Clustered Execution Cores,"
HPS Technical Report, TR-HPS-2004-001, May 2004.

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