HPS Research Group

Other Microarchitecture Publications

Stephen Pruett and Yale Patt,

"Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches,"

The 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Aniket Deshmukh and Yale Patt,

"Criticality Driven Fetch,"

The 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Siavash Zangeneh, Stephen Pruett, Sangkug Lym, and Yale Patt,

"BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches,"

The 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Ben (Ching-Pei) Lin, Michael B. Healy, Rustam Miftakhutdinov, Philip G. Emma, and Yale Patt,

"Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts via Data Duplication,"

The 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Milad Hashemi, Onur Mutlu, and Yale N. Patt,

"Continuous Runhaead: Transparent Hardware Acceleration for Memory Intensive Workloads,"

The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt,

"Accelerating Dependent Cache Misses with an Enhanced Memory Controller,"

The 43rd ACM/IEEE International Symposium on Computer Architecture (ISCA)

Milad Hashemi, and Yale N. Patt,

"Filtered Runahead Execution with a Runahead Buffer,"

The 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Milad Hashemi, Debbie Marr, Doug Carmean, and Yale N. Patt,

"Efficient Execution of Bursty Applications,"

IEEE Computer Architecture Letters (CAL)

Khubaib, M. Aater Suleman, Milad Hashemi, Chris Wilkerson, Yale N. Patt,

"MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP,"

Proceedings of the 45th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO)

Rustam Miftakhutdinov, Eiman Ebrahimi, Yale N. Patt,

"Predicting Performance Impact of DVFS for Realistic Memory Systems,"

Proceedings of the 45th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO)

Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,

"Prefetch-Aware Shared-Resource Management for Multi-Core Systems,"

Proceedings of the 38th International Symposium on Computer Architecture (ISCA)

M. Aater Suleman, Moinuddin K. Qureshi, Khubaib, and Yale N. Patt,

"Feedback-Directed Pipelined Parallelism"

Proceedings of the 19th International Conference on Parallel Architecture and Compilation Techniques (PACT)

M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, and Yale N. Patt,

"Data Marshaling for Multi-core Architectures"

Proceedings of the 37th International Symposium on Computer Architecture (ISCA)

Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,

"Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems"

Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

Chang Joo Lee, Veynu Narasiman, Onur Mutlu, and Yale N. Patt,

"Improving Memory Bank-Level Parallelism in the Presence of Prefetching"

Proceedings of the 42nd International Symposium on Microarchitecture (MICRO)

Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, and Yale N. Patt,

"Coordinated Control of Multiple Prefetchers in Multi-Core Systems"

Proceedings of the 42nd International Symposium on Microarchitecture (MICRO)

José A. Joao, Onur Mutlu, and Yale N. Patt,

"Flexible Reference-Counting-Based Hardware Acceleration for Garbage Collection,"

Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA)

M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, and Yale N. Patt,

"Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures"

Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt,

"Techniques for Bandwidth-Efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems"

Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA)

Chang Joo Lee, Onur Mutlu, Veynu Narasiman, and Yale N. Patt,

"Prefetch-Aware DRAM Controllers"

Proceedings of the 41st International Symposium on Microarchitecture (MICRO)

Chang Joo Lee, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,

"Performance-Aware Speculation Control using Wrong Path Usefulness Prediction"

Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA)

Onur Mutlu, Hyesoon Kim, and Yale N. Patt,

"Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance"

IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS)

Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,

"An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors,"

IEEE Transactions on Computers (TC)

Onur Mutlu, Hyesoon Kim, and Yale N. Patt,

"Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns,"

Proceedings of the 38th ACM/IEEE International Symposium on Microarchitecture

Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,

"Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References,"

International Journal of Parallel Programming (IJPP)

Moinuddin K. Qureshi, Onur Mutlu, and Yale N. Patt,

"Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors,"

Proceedings of the International Conference on Dependable Systems and Networks

Onur Mutlu, Hyesoon Kim, and Yale N. Patt,

"Techniques for Efficient Processing in Runahead Execution Engines,"

Proceedings of the 32nd International Symposium on Computer Architecture

Moinuddin K. Qureshi, David Thompson, and Yale N. Patt,

"The V-Way Cache: Demand Based Associativity via Global Replacement,"

Proceedings of the 32nd International Symposium on Computer Architecture

Onur Mutlu, Hyesoon Kim, Jared Stark, and Yale N. Patt,

"On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor,"

Computer Architecture Letters

Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,

"Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance,"

Proceeedings of the 16th Symposium on Computer Architecture and High Performance Computing

Mary D. Brown and Yale N. Patt,

"Demand-Only Broadcast: Reducing Register File and Bypass Power in Clustered Execution Cores,"

Proceedings of the First Watson Conference on Interaction between Architecture, Circuits, and Compilers

Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,

"Understanding The Effects of Wrong-path Memory References on Processor Performance,"

Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction with 31st International Symposium on Computer Architecture

Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,

"Runahead Execution: An Effective Alternative to Large Instruction Windows,"

IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences

Paul Racunas and Yale N. Patt,

"Partitioned first-level cache design for clustered microarchitectures,"

Proceedings of the 17th Annual International Conference on Supercomputing

Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,

"Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,"

Proceedings of the 9th International Symposium on High-Performance Computer Architecture

Mary D. Brown and Yale N. Patt,

"Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files,"

Proceedings of the 8th International Symposium on High-Performance Computer Architecture

Mary D. Brown, Jared Stark, and Yale N. Patt,

"Select-Free Instruction Scheduling Logic,"

Proceedings of the 34th ACM/IEEE International Symposium on Microarchitecture

Jared Stark, Mary D. Brown, and Yale N. Patt,

"On Pipelining Dynamic Instruction Scheduling Logic,"

Proceedings of the 33rd ACM/IEEE International Symposium on Microarchitecture

Eric Hao, Po-Yung Chang, Marius Evers, and Yale N. Patt,

"Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures,"

International Journal of Parallel Programming

Jared Stark, Paul B. Racunas, and Yale N. Patt,

"Reducing the Performance Impact of ICache Misses by Writing Instructions into the Reservation Stations Out-of-Order,"

Proceedings of the 30th ACM/IEEE International Symposium on Microarchitecture

Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, and Jared Stark,

"One Billion Transistors, One Uniprocessor, One Chip,"

Eric Hao, Po-Yung Chang, Marius Evers, and Yale N. Patt,

"Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures,"

Proceedings of the 29th ACM/IEEE International Symposium on Microarchitecture

Yale N. Patt,

"The Microprocessor for Scientific Computing in the year 2000,"

IEEE Computational Science and Engineering

Yale Patt,

"First, Let's Get the Uniprocessor Right,"

MicroDesign Resources, Microprocessor Report

Stephen Melvin and Yale N. Patt,

Enhancing Instruction Scheduling With a Block-Structured ISA,

International Journal of Parallel Programming

Eric Sprangle and Yale N. Patt,

"Facilitating Superscalar Processing via a Combined Static/Dynamic Register Renaming Scheme,"

Proceedings of the 27th International Symposium on Microarchitecture

Michael Butler and Yale Patt,

"A Comparative Performance Evaluation of Various State maintenance Mechanisms,"

Proceedings of the 26th International Symposium and workshop on Microarchitecture

Michael Butler and Yale Patt,

"An Investigation of the Performance of Various Dynamic Scheduling Techniques,"

Proceedings, 25th International Symposium and workshop on Microarchitecture

Tse-Yu Yeh and Yale Patt,

"A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution,"

Proceedings, 25th International Symposium and workshop on Microarchitecture

Michael Butler, David Dyer, and Yale Patt,

"Toward the Specification of an ISA for High Performance Computing Engines -- Part I: The Hardware Perspective,"

Proceedings, 25th Hawaii International Conference on Systems Sciences

Michael Butler and Yale Patt,

"The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling,"

Proceedings, 24th International Symposium and workshop on Microarchitecture

M. Butler, T-Y Yeh, Y. Patt, M. Alsup, H. Scales, and M. Shebanow,

"Single Instruction Stream Parallelism is Greater than Two,"

Proceedings of the 18th International Symposium on Computer Architecture

Stephen Melvin and Yale Patt,

"Exploiting Fine-Grained Parallelism through Combined Hardware and Software Techniques,"

Proceedings of the 18th International Symposium on Computer Architecture

Michael Butler and Yale Patt,

"An Area-efficient Register Alias Table for Implementing HPS,"

Proceedings of the International Conference on Parallel Processing

Yale Patt,

"Microarchitecture choices (implementation of the VAX),"

Proceedings of the 22nd annual international workshop on Microprogramming and Microarchitecture

Stephen W. Melvin and Yale Patt,

"Performance benefits of large execution atomic units in dynamically scheduled machines"

Proceedings of the 3rd international conference on Supercomputing

Ashok Singhal and Yale Patt,

"A high performance Prolog processor with multiple function units,"

Proceedings of the 16th International Symposium on Computer Architecture

John A. Swensen and Yale Patt,

"Hierarchical registers for scientific computers,"

Proceedings of the 2nd international conference on Supercomputing

Ashok Singhal and Yale Patt,

"Implementing a Prolog machine with multiple functional units,"

Proceedings of the 21st annual international workshop on Microprogramming and Microarchitecture

Stephen W. Melvin, Michael C. Shebanow, and Yale Patt,

"Hardware support for large atomic units in dynamically scheduled machines,"

Proceedings of the 21st annual international workshop on Microprogramming and Microarchitecture

Wen-mei W. Hwu and Yale Patt,

"Checkpoint repair for out-of-order execution machines,"

Proceedings of the 14th International Symposium on Computer Architecture

John Swensen and Yale Patt,

"Fast temporary storage for serial and parallel execution,"

Proceedings of the 14th International Symposium on Computer Architecture

Stephen W. Melvin and Yale Patt,

"A clarification of the dynamic/static interface,"

Proceedings of the 20th Annual Hawaii International Conference on System Sciences

Wen-mei W. Hwu and Yale Patt,

"Exploiting horizontal and vertical concurrency via the HPSm microprocessor,"

Proceedings of the 20th annual workshop on Microprogramming

James E. Wilson, Steve Melvin, Michael Shebanow, Wen-mei Hwu, and Yale Patt,

"On tuning the microarchitecture of an HPS implementation of the VAX,"

Proceedings of the 20th annual workshop on Microprogramming

Stephen W. Melvin and Yale Patt,

"SPAM: a microcode based tool for tracing operating system events,"

Proceedings of the 20th annual workshop on Microprogramming

Jeff Gee, Stephen W. Melvin and Yale Patt,

"The implementation of Prolog via VAX 8600 microcode,"

Proceedings of the 19th annual workshop on Microprogramming

Yale Patt, Stephen W. Melvin, Wen-mei Hwu, Michael C. Shebanow, Chien Chen, and Jiajuin Wei

"Run-time generation of HPS microinstructions from a VAX instruction stream,"

Proceedings of the 19th annual workshop on Microprogramming

Stephen W. Melvin and Yale Patt,

"A microcode-based environment for noninvasive performance analysis,"

Proceedings of the 19th annual workshop on Microprogramming

Wen-mei Hwu and Yale Patt,

"HPSm, a high performance restricted data flow architecture having minimal functionality,"

Proceedings of the 13th International Symposium on Computer Architecture

Barry Fagin, Yale Patt, Vason Srini, and Alvin Despain

"Compiling Prolog into microcode: a case study using the NCR/32-000,"

Proceedings of the 18th annual workshop on Microprogramming

Yale Patt, Wen-mei Hwu, and Michael Shebanow

"HPS, a new microarchitecture: rationale and introduction,"

Proceedings of the 18th annual workshop on Microprogramming

Yale Patt, Stephen W. Melvin, Wen-mei Hwu, and Michael Shebanow

"Critical issues regarding HPS, a high performance microarchitecture,"

Proceedings of the 18th annual workshop on Microprogramming

Yale Patt and John K. Ahlstrom

"Microcode and the protection of intellectual effort,"

Proceedings of the 18th annual workshop on Microprogramming

Other Microarchitecture Publications

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